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III/V FET-on-Si

Downscaling the size of transistors in today’s CMOS chips is reaching its physical limits, hence the established way to increase the computing power of chips will come to an end. In order to overcome this barrier the next generation of chips will contain III/V semiconductor-based transistors with much higher carrier mobility compared to Si and, thus, enabling higher operation frequencies.
The implementation of such transistors requires the low defect-density deposition of the III/V channel material on CMOS Si substrates. Applying the proprietary GaP-on-Si-template technology NAsPIII/V, based on the long term experience in the growth of III/V semiconductors, developed thin In- as well as As-free metamorphic relaxation-buffer layers, on which  specific III/V-FET channel layers, featuring low defect density and high carrier mobility, can be deposited.

© NAsP 2018