GaP-on-Si-template technology

In collaboration with the Material Sciences Center at the Philipps-University,  NAsP_III/V has overcome the first challenge for the integration of a variety of III/V-semiconductor materials and device heterostructures on CMOS-compatible (001) Si wafers by the development of a proprietary nucleation process for the deposition of thin GaP layers on 300mm Si (001) substrates (as used in the Si-CMOS industry) with high crystalline perfection. These GaP-on-Si-template layers are free of dislocations, stacking faults and twins and possess an anti-phase domain (APB) free surface with excellent smooth surface morphologies [publications].

These high-quality GaP-on-Si-template structures serve as perfect basis for the subsequent integration of a variety of III/V-material systems on (001) Si-substrates for laser, electronic as well as solar cell or quantum technology applications. Based on this broad experience NAsP_III/V will support your company with individual developments for your specific applications. For a detailed advice or request for this GaP-on-Si-template technology please contact us [info@nasp.de].